package SimpleLACore

import chisel3.stage._

object GenRAM {
  def main(args: Array[String]): Unit = {
    (new ChiselStage).execute(Array("--target-dir", "build"), Seq(ChiselGeneratorAnnotation(() => new SimpleLACoreWrapRAM)))
  }
}
object GenAXI {
  def main(args: Array[String]): Unit = {
    (new ChiselStage).execute(Array("--target-dir", "build"), Seq(ChiselGeneratorAnnotation(() => new SimpleLACoreTopAXI)))
  }
}
object GenSRAM {
  def main(args: Array[String]): Unit = {
    (new ChiselStage).execute(Array("--target-dir", "build"), Seq(ChiselGeneratorAnnotation(() => new SimpleLACoreTopSRAM)))
  }
}